Cache Behavior of Network Protocols

In this paper we present a performance study of memory reference behavior in network protocol processing, using an Internet-based protocol stack implemented in the x-kernel running in user space on a MIPS R4400-based Silicon Graphics machine. We use the protocols to drive a validated execution-driven architectural simulator of our machine. We characterize the behavior of network protocol processing, deriving statistics such as cache miss rates and percentage of time spent waiting for memory. We also determine how sensitive protocol processing is to the architectural environment, varying factors such as cache size and associativity, and predict performance on future machines. We show that network protocol cache behavior varies widely, with miss rates ranging from 0 to 28 percent, depending on the scenario. We find instruction cache behavior has the greatest effect on protocol latency under most cases, and that cold cache behavior is very different from warm cache behavior. We demonstr...

• Type: Conference
• Year: 1997
• Where: SIGMETRICS
• Authors: Erich M. Nahum, David J. Yates, James F. Kurose, Donald F. Towsley
• Keywords: Cache Behavior, Hardware, Network Protocol, Protocol Processing, SIGMETRICS 1997