A RISC Processor with Extended Forwarding

The paper examines a simple conceptual modification of the operation unit of a RISC processor. We propose to substitute a part of the conventional general purpose register file by a shift register for all operation results. The presented approach allows to reduce the instruction size for a great deal of instructions and so the instruction stream, and it is also a promising approach to make the processor architecture more regular.

• Type: Conference
• Year: 1997
• Where: ARCS
• Authors: Gert Markwardt, Günter Kemnitz, Rainer G. Spallek
• Keywords: ARCS 1997, Purpose Register File, RISC Processor, Simple Conceptual Modification, Software Engineering