Latch Redundancy Removal Without Global Reset

For circuits where there may be latches with no reset line, we show how to replace some of them with combinational logic. All previous work in sequential optimization by latch removal assumes a designated initial state. Without this assumption, the design can power up in any state and earlier techniques are not applicable. We present an algorithm for identifying and replacing redundant latches by combinational logic such that no environment of the design can detect the change. The new design preserves the steady state behavior as well as all initializing sequences of the old design. We report experimental results on benchmark circuits and demonstrate savings in area without adverse impact on delay.

• Type: Conference
• Year: 1996
• Where: ICCD
• Authors: Shaz Qadeer, Robert K. Brayton, Vigyan Singhal
• Keywords: Combinational Logic, Hardware, ICCD 1996, Redundant Latches, Steady State Behavior