Implementation of a SliM Array Processor

This paper presents the design and implementation of a Sliding Memory Plane (SliM) Array Processor, a mesh-connected SIMD architecture. To build the array processor, we developed the SliM chip consisting of mesh-connected 5 x 5 processing elements (PEs). Due to the idea of sliding, that is, overlapping the inter-PE communication with the computation, the SliM chip can greatly reduce the inter-PE communication overhead, a disadvantage of existing SIMD array processors. This paper addresses architectures and implementation issues of the SliM chip and the SliM Array Processor. The chip operates at 25 MHz and gives 625 MIPS. We implemented the protype SliM Array Processor for realtime image processing.

• Type: Conference
• Year: 1996
• Where: IPPS
• Authors: Hyun M. Chang, Myung Hoon Sunwoo, Tai-Hoon Cho
• Keywords: Array Processor, Distributed And Parallel Computing, IPPS 1996, SliM Array Processor, SliM Chip