Performance Comparison of ILP Machines with Cycle Time Evaluation

Many studies have investigated performance improvement through exploiting instruction-level parallelism (ILP) with a particular architecture. Unfortunately, these studies indicate performance improvement using the number of cycles that are required to execute a program, but do not quantitatively estimate the penalty imposed on the cycle time from the architecture. Since the performance of a microprocessor must be measured by its execution time, a cycle time evaluation is required as well as a cycle count speedup evaluation. Currently, superscalar machines are widely accepted as the machines which achieve the highest performance. On the other hand, because of hardware simplicity and instruction scheduling sophistication, there is a perception that the next generation of microprocessors will be implemented with a VLIW architecture. A simple VLIW machine, however, has a serious weakness regarding speculative execution. Thus, it is a question whether a simple VLIW machine really outperfor...

• Type: Conference
• Year: 1996
• Where: ISCA
• Authors: Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya
• Keywords: Cycle Count Speedup, Hardware, ISCA 1996, Simple Vliw Machine, VLIW Machine