On test coverage of path delay faults

W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and a falling transition. However, the test criterion is different from that of the slow-to-rise and slow-to-fall transition faults. The test, called "line delay test", as a path delay test for the longest sensitizable path producing a given transition on the target line. The maximum number of tests (and faults) is limited to twice the number of lines. However, the line delay test criterion resembles path delay test and not the gate or transition delay test. Using a two-pass test generation procedure, we begin with a minimal set of longest paths covering all lines and generate tests for them. Fault simulation is used to determine the coverage metric. For uncovered lines, an the second pass, several paths of decreasing length are targeted. W e present a theorem stating that a redundant stuck-at fault mak...

• Type: Conference
• Year: 1996
• Where: VLSID
• Authors: Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal
• Keywords: Delay Test, Path Delay, Path Delay Test, VLSI, VLSID 1996