A general state graph transformation framework for asynchronous synthesis

Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well as new state signal insertion during the transformation process. Considering concurrency reduction in the exploration space is crucial because more area efficient and higher performancecircuits may be possible. This is partly because often fewer new state signals are required and the resulting logic is typically more highly unspecified, thus leaving more room for optimizations at the logic level. Considering new state signal insertion is also crucial as new signals are usually required for disambiguating state coding conflicts. A larger solution space can be searched when both classes of transformations are considered. The new framework has been implemented and verified on a large set of realistic design examples.

• Type: Conference
• Year: 1994
• Where: EURODAC
• Authors: Bill Lin, Chantal Ykman-Couvreur, Peter Vanbekbergen
• Keywords: Concurrency Reduction, EURODAC 1994, State Graph Level, State Signal Insertion, VHDL