A VHDL-based bus model for multi-PCB system design

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In the development of bus-based systems and individual PCB boards interfacing to a bus, the simulation usually requires a specific test bench or creation of quite complex stimuli. This problem can be avoided with a VHDL model of the bus. In this paper, the bus model concept is discussed. The concept can be applied to serial and parallel, single and multiple master bus modeling on various hierarchical levels. The model includes timing and signaling analysis, master, slave and arbitration modules. ISA (PC/AT) bus is used as an example case of the modeling.

Jari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuo

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Bus Model Concept | EURODAC 1994 | Individual Pcb Boards | Master Bus Modeling | VHDL |

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Added	08 Aug 2010
Updated	08 Aug 2010
Type	Conference
Year	1994
Where	EURODAC
Authors	Jari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuominen

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A VHDL-based bus model for multi-PCB system design

Bus Model Concept | EURODAC 1994 | Individual Pcb Boards | Master Bus Modeling | VHDL |

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