Exact path sensitization in timing analysis

of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in comparison with all other approaches, since these are based on approximations of this criterion. Timing verification is an important aspect in chip design. However, the growing complexity of combinational circuits increases the total number of false paths, which demands fast and accurate false path elimination methods. Several approaches have been presented in literature, but all are based on approximations of the exact criterion, and offer no exact results. This paper presents the first implementation of the exact criterion. Experiments show that this tool is much more accurate in comparison with other approaches. The rest of this paper is organized as follows. Section 2 discusses the exact and other criteria. A description of the proposed algorithm is given in section 3. Then the two steps responsible for eliminatin...

• Type: Conference
• Year: 1994
• Where: EURODAC
• Authors: R. Peset Llopis
• Keywords: EURODAC 1994, Exact Criterion, False Paths, Path Finding Tool, VHDL