Input don't care sequences in FSM networks

Current approaches to compute and exploit the flexibility of a component in an FSM network are all at the symbolic level [23, 30, 33, 31]. Conventionally, exploitation of this flexibility relies on state minimizers for incompletely specified FSM’s (ISFSM’s) or pseudo non-deterministic FSM’s (PNDFSM’s) [33]. However, state-of-theart state minimizers cannot handle large ISFSM’s or PNDFSM’s [12, 14, 34, 8, 15]. In addition, these exploitation techniques are at the symbolic level, not directly at the net-list logic level. We present a general approach to exploit exact or approximate flexibility directly at the net-list logic level, and we demonstrate that many sequential logic optimization techniques can be applied in exploitation. Moreover, we propose a new procedure for input don’t care sequences. As a result, both computation and exploitation of input don’t care sequences in larger FSM networks can be made efficient and effective. Finally, we give preliminary resul...

• Type: Conference
• Year: 1993
• Where: ICCAD
• Authors: Huey-Yih Wang, Robert K. Brayton
• Keywords: Fsm Network, Hardware, ICCAD 1993, Net-list Logic Level, State Minimizers