Synthesis of Controllers from Interval Temporal Logic Specification

for a state machine which is an abstraction for an existing sequential circuit, which can be useful for redesign or engineering change. The generated state machines can be further processed by logic synthesizer, such as SIS. We present experimental results and show the usefulnessof our method. Keyword: temporal logic, logic synthesis

• Type: Conference
• Year: 1993
• Where: ICCD
• Authors: Masahiro Fujita, Shinji Kono
• Keywords: Generated State Machines, Hardware, ICCD 1993, Logic Synthesizer, State Machines