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MICRO
1993
IEEE

Techniques for extracting instruction level parallelism on MIMD architectures

14 years 3 months ago
Techniques for extracting instruction level parallelism on MIMD architectures
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIMD architectures to allow them to extract the instruction level parallelism achieved by current superscalar and VLIW machines. A new architecture is proposed which utilizes the advantages of a multiple instruction stream design while addressing some of the limitations that have prevented MIMD architectures from performing ILP operation. A new code scheduling mechanism is described to support this new architecture by partitioning instructions across multiple processing elements in order to exploit this level of parallelism.
Gary S. Tyson, Matthew K. Farrens
Added 09 Aug 2010
Updated 09 Aug 2010
Type Conference
Year 1993
Where MICRO
Authors Gary S. Tyson, Matthew K. Farrens
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