Building Multithreaded Architectures with Off-the-Shelf Microprocessors

Present-day parallel computers often face the problems of large software Overheadsfor process switching and interprocessor communication. These problems are addressed by the Multi- Threaded Architecture (MTA), a multiprocessor model designed for eficient parallel ezecution of both numerical and non-numerical programs. We begin with a conventional processor, and add what we believe to be the minimal ezternal hardware necessaryfor eficient support of multithreadedprograms. The presentation begins with the top-level architecture and the program ezecution model. The latter includes a description of activation frames and thread synchronization. This is followed by a detailed presentation of the processor. Major features of the MTA include the RegisterUse Cache for ezploiting temporal locality in multiple register set microprocessors, support for progmms requiring non-determinism and speculation, and local function invocations which can utilize registers for parameter passing.

• Type: Conference
• Year: 1994
• Where: IPPS
• Authors: Herbert H. J. Hum, Kevin B. Theobald, Guang R. Gao
• Keywords: Distributed And Parallel Computing, Eficient Parallel Ezecution, IPPS 1994, Minimal Ezternal Hardware, Present-day Parallel Computers