A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs

In this paper, we propose an architecture synthesis methodolog `to realize cascaded Infinite Impulse Response (IIRJfilter in Table Look Up (TLU) Field Progmmmable Gate A m y s (FPGA). The synthesis procedure involves a systematic tmnsfomation of the Dependance Graph (DG) corresponding to the cascaded IIR filter to a Papelined Fized Full Size A+ my (PFFSA). We ofler an implementation of a cascaded 8th order IIR filters on Xilinz XC3090 FPGA devices.

• Type: Conference
• Year: 1994
• Where: VLSID
• Authors: G. N. Rathna, S. K. Nandy, K. Parthasarathy
• Keywords: Architecture Synthesis Methodolog, Iir Filters, Infinite Impulse Response, VLSI, VLSID 1994