Analysis of Multithreaded Architectures for Parallel Computing

Multithreading has been proposed as an architectural strategy for tolerating latency in multiprocessors and, through limited empirical studies, shown to offer promise. This paper develops an analytical model of multithreaded processor behavior based on a small set of architectural and program parameters. The model gives rise to a large Markov chain, which is solved to obtain a formula for processor efficiency in terms of the number of threads per processor, the remote reference rate, the latency, and the cost of switching between threads. It is shown that a multithreaded processor exhibits three operating regimes: linear (efficiency is proportional to the number of threads), transition, and saturation (efficiency depends only on the remote reference rate and switch cost). Formulae for regime boundaries are derived. The model is embellished to reflect cache degradation due to multithreading, using an analytical model of cache behavior, demonstrating that returns diminish as the number ...

• Type: Conference
• Year: 1990
• Where: SPAA
• Authors: Rafael H. Saavedra-Barrera, David E. Culler, Thorsten von Eicken
• Keywords: Distributed And Parallel Computing, Model, Multithreaded Processor, Remote Reference Rate, SPAA 1990