Scalable High Throughput and Power Efficient IP-Lookup on FPGA

Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmable Gate Arrays (FPGAs), state-of-theart designs cannot support the current largest routing table (consisting of 257K prefixes in backbone routers). We propose a novel scalable high-throughput, low-power SRAMbased linear pipeline architecture for IP lookup. Using a single FPGA, the proposed architecture can support the current largest routing table, or even larger tables of up to 400K prefixes. Our architecture can also be easily partitioned, so as to use external SRAM to handle even larger

• Type: Conference
• Year: 2009
• Where: FCCM
• Authors: Hoang Le, Viktor K. Prasanna
• Keywords: Available On-chip Memory, FCCM 2009, Largest Routing Table, Programmable Gate Arrays, VLSI