VHC: Quickly Building an Optimizer for Complex Embedded Architectures

To meet the high demand for powerful embedded processors, VLIW architectures are increasingly complex (e.g., multiple clusters), and moreover, they now run increasingly sophisticated control-intensive applications. As a result, developing architecture-specific compiler optimizations is becoming both increasingly critical and complex, while timeto-market constraints remain very tight. In this article, we present a novel program optimization approach, called the Virtual Hardware Compiler (VHC), that can perform as well as static compiler optimizations, but which requires far less compiler development effort, even for complex VLIW architectures and complex target applications. The principle is to augment the target processor simulator with superscalar-like features, observe how the target program is dynamically optimized during execution, and deduce an optimized binary for the static VLIW architecture. Developing an architecture-specific optimizer then amounts to modifying the processor ...

• Type: Conference
• Year: 2004
• Where: CGO
• Authors: Michael Dupré, Nathalie Drach, Olivier Temam
• Keywords: CGO 2004, Compiler Optimizations, Software Engineering, Static Compiler Optimizations, Vliw Architecture