Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit

In this paper, we propose a reconfigurable hardware accelerator for fixed-point-matrix-vector-multiply/add operations, capable to work on dense and sparse matrices formats. The prototyped hardware unit accommodates 4 dense or sparse matrix inputs and performs computations in a space parallel design achieving 4 multiplications and up to 12 additions at 120 MHz over an xc2vp100-6 FPGA device,

• Type: Conference
• Year: 2006
• Where: ASAP
• Authors: Humberto Calderon, Stamatis Vassiliadis
• Keywords: ASAP 2006, Hardware, Reconfigurable Hardware Accelerator, Sparse Matrices Formats, Sparse Matrix Inputs