Timing-Sensitive Information Flow Analysis for Synchronous Systems

Timing side channels are a serious threat to the security of cryptographic algorithms. This paper presents a novel method for the timing-sensitive analysis of information flow in synchronous hardware circuits. The method is based on a parameterized notion of confidentiality for finite transition systems that allows one to model information leakage in a fine-grained way. We present an efficient decision procedure for system security and apply it to discover timing leaks in nontrivial hardware implementations of cryptographic algorithms.

• Type: Conference
• Year: 2006
• Where: ESORICS
• Authors: Boris Köpf, David A. Basin
• Keywords: Cryptographic Algorithms, ESORICS 2006, Nontrivial Hardware Implementations, Security Privacy, Synchronous Hardware Circuits