Retargetable Cache Simulation Using High Level Processor Models

During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simulator. The cache simulator has been implemented using a retargetable instruction set simulator from the SimnML [9] processor description language. The retargetability helps in cache simulation and evaluation much before the actual processor design.

• Type: Conference
• Year: 2001
• Where: APCSAC
• Authors: Rajiv A. Ravindran, Rajat Moona
• Keywords: APCSAC 2001, Cache Simulator, Computer Architecture, Multiple Cache Configurations, Retargetable On-line Cache