An efficient solution to the storage correspondence problem for large sequential circuits

Abstract- Traditional state-traversal-basedmethods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if the correspondence of the memory elements of the two circuits can be established, a difficult sequential verification problem can be transformed into an easier combinational verification problem. In this paper, we propose an approach that combines two complementary simulation-based methods forfast and accurate storage correspondence. Experiments on the large ISCASS9 benchmark circuitsdemonstratethe superiority.

• Type: Conference
• Year: 2001
• Where: ASPDAC
• Authors: Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee
• Keywords: ASPDAC 2001, Hardware, Memory Elements, Sequential Verification Problem, Verification Problem