Power optimization and management in embedded systems

Power-efficient design requires reducing power dissipation in all parts of the design and during all stages of the design process subject to constraints on the system performance and quality of service (QoS). Power-aware high-level language compilers, dynamic power management policies, memory management schemes, bus encoding techniques, and hardware design tools are needed to meet these often-conflicting design requirements. This paper reviews techniques and tools for power-efficient embedded system design, considering the hardware platform, the application software, and the system software. Design examples from an Intel StrongARM based system are provided to illustrate the concepts and the techniques. This paper is not intended as a comprehensive review, rather as a starting point for understanding poweraware design methodologies and techniques targeted toward embedded systems.

• Type: Conference
• Year: 2001
• Where: ASPDAC
• Authors: Massoud Pedram
• Keywords: ASPDAC 2001, Bus Encoding Techniques, Design, Hardware, Hardware Design Tools