Transparent data-memory organizations for digital signal processors

Today's digital signal processors (DSPs), unlike general-purpose processors, use a non-uniform addressing model in which the primary components of the memory system--the DRAM and dual tagless SRAMs--are referenced through completely separate segments of the address space. The recent trend of programming DSPs in highlevel languages instead of assembly code has exposed this memory model as a potential weakness, as the model makes for a poor compiler target. In many of today's high-performance DSPs this non-uniform model is being replaced by a uniform model--a transparent organization like that of most general-purpose systems, in which all memory structures share the same address space as the DRAM system. In such a memory organization, one must replace the DSP's tagless SRAMs with something resembling a general-purpose cache. This study investigates the performance of a range of traditional and slightly non-traditional cache organizations for a high-performance DSP, the Te...

• Type: Conference
• Year: 2001
• Where: CASES
• Authors: Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob
• Keywords: CASES 2001, Dsp's Tagless Srams, Non-traditional Cache Organizations, System Software, Tagless Sram