Generating highly-routable sparse crossbars for PLDs

A method for evaluating and constructing sparse crossbars which are both area efficient and highly routable is presented. The evaluation method uses a network flow algorithm to accurately compute the percentage of random test vectors that can be routed. The construction method attempts to maximize the spread of the switch locations, such that any given subset of input wires can connect to as many output wires as possible. Based on Hall's Theorem, we argue that this increases the likelihood of routing. The hardest test vectors to route are those which attempt to use all of the crossbar outputs. Results in this paper show that areaefficient sparse crossbars can be constructed by providing more outputs than required and a sufficient number of switches. In a few specific case studies, it is shown that sparse crossbars with about 90% fewer switches than a full crossbar can be constructed, and these crossbars are capable of routing over 95% of randomly chosen routing vectors. In one ca...

• Type: Conference
• Year: 2000
• Where: FPGA
• Authors: Guy G. Lemieux, Paul Leventis, David M. Lewis
• Keywords: FPGA, FPGA 2000, Random Test Vectors, Sparse Crossbars, Test Vectors