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FPL
2000
Springer

Evaluation of Accelerator Designs for Subgraph Isomorphism Problem

14 years 2 months ago
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem
Many applications can be modeled as subgraph isomorphism problems. However, this problem is generally NP-complete and difficult to compute. A custom computing circuit is a prospective solution for such problems. This paper examines various accelerator designs, and compares them quantitatively from two points of view: cost and performance. An algorithm that is suited for hardware implementation is also proposed. The hardware for the proposed algorithm is much smaller on logic scale, and operates at a higher frequency than Ullmann's design. The prototype accelerator operates at 16.5 MHz on a Lucent ORCA 2C15A, which outperforms the software implementation of Ullmann's algorithm on a 400 MHz Pentium II.
Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangth
Added 24 Aug 2010
Updated 24 Aug 2010
Type Conference
Year 2000
Where FPL
Authors Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi
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