A Self-Reconfigurable Gate Array Architecture

Abstract. This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chip configuration/data memory. These two features are necessary for efficient self-reconfiguration and are useful in general as well--no other device offers both features. The enhanced context switching feature permits arbitrary regions of the chip to selectively context switch--its not necessary for the whole device to do so. The memory access feature allows data transfer between logic cells and memory locations, and also directly between memory locations. The key innovation enabling the above features is the use of a mesh of trees based interconnect with logic cells and memory blocks at the leaf nodes and identical switches at other nodes. The mesh of trees topology allows a logic cell to be associated with a pair of switches. The logic cell and the switches can be placed close to the memory block that stores...

• Type: Conference
• Year: 2000
• Where: FPL
• Authors: Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro Mei, Viktor K. Prasanna
• Keywords: Context Switching, FPL 2000, Hardware, Logic Cell, Memory Access