Dynamic Optimisation of Non-linear Feed Forward Circuits

Abstract. An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells, of the interconnection topologies and of the interconnections among cells. This circuit is readily applicable to the design of set-associative cache memories, with on-line tuning of the function during cache operation.

• Type: Conference
• Year: 2000
• Where: ICES
• Authors: Ernesto Damiani, Valentino Liberali, Andrea Tettamanzi
• Keywords: 16-bit Address Space, Hardware, ICES 2000, Set-associative Cache Memories, Simple Hash Function