Hardware Prediction for Data Coherency of Scientific Codes on DSM

This paper proposes a hardware mechanism for reducing coherency overhead occurring in scientific computations within DSM systems. A first phase aims at detecting, in the address space regular patterns (called streams) of coherency events (such as requests for exclusive, shared or invalidation). Once a stream is detected at a loop level, regularity of data access can be exploited at the loop level (spatial locality) but also between loops (temporal locality). We present a hardware mechanism capable of detecting and exploiting efficiently these regular patterns. Expectable benefits as well as hardware complexity are discussed and the limited drawbacks and potential overheads are exposed. For a benchmarks suite of typical scientific applications results are very promising both in terms of coherency streams and the effectiveness of our optimizations.

• Type: Conference
• Year: 2000
• Where: SC
• Authors: Jean-Thomas Acquaviva, William Jalby
• Keywords: Applied Computing, Hardware Mechanism, Loop Level, Regular Patterns, SC 2000