Power Estimation in Sequential Circuits

Abstract A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow e cient power estimation for the whole design. An important advantage of this approach is that the desired accuracy can be speci ed up-front by the user; the algorithm iterates until the speci ed accuracy is achieved. This has been implemented and tested on a number of sequential circuits and found to be much faster than existing techniques. We can complete the analysis of a circuit with 1,452 ip- ops and 19,253 gates in about 4.6 hours the largest test case reported previously has 223 ip- ops.

• Type: Conference
• Year: 1995
• Where: DAC
• Authors: Farid N. Najm, Shashank Goel, Ibrahim N. Hajj
• Keywords: Computer Architecture, DAC 1995, Power Estimation, Sequential Circuits, Statistical Estimation Technique