Design of FPGAs with Area I/O for Field Programmable MCM

Area-IO provide a way to eliminate the IO bottleneck of eld programmable logic devices (FPLDs) created the mismatch between the ability of perimeter bonds to provide IO and and the propensity of logic to demand it. Whether the incorporation of area IO into FPLD architectures has undesirable side eects is a question that has not yet been answered. In this paper, we examine the architectural impact of area-IO on FPLDs from a theoretical and experimental standpoint and show that the

• Type: Conference
• Year: 1995
• Where: FPGA
• Authors: Vijayshri Maheshwari, Joel Darnauer, John Ramirez, Wayne Wei-Ming Dai
• Keywords: Area Io, Eld Programmable Logic, FPGA, FPGA 1995, IO Bottleneck