Some Notes on Power Management on FPGA-Based Systems

Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuumtube electronics [1], the increasing clock frequency and gate density of the current integrated circuits has appended power consumption to traditional design trade-offs. This paper explore the usefullness of some low-power design methods based on architectural and implementation modifications, for FPGAbased electronic systems. The contribution of spurious transitions to the overal consumption is evidenced and main strategies for its reduction are analized. The efectiveness of pipelining and partitioning inprovements as low-power design methodologies are quantified by case-studies based on array multipliers. Moreover, a methodology suitable for FPGAs power analysis is presented.

• Type: Conference
• Year: 1995
• Where: FPL
• Authors: Eduardo I. Boemo, Guillermo González de Rivera, Sergio López-Buedo, Juan M. Meneses
• Keywords: FPL 1995, Hardware, Low-power Design, Low-power Design Methods, Traditional Design Trade-offs