A delay model for logic synthesis of continuously-sized networks

ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as constant and makes the cell's delay a linear function of load. Our model is based on a different, but equally fundamental linearity in the equation relating area, delay, and load: namely, we may keep a cell's delay constant by making its area a linear function of load. This allows us to technology map using a library with continuous device sizing, satisfies certain electrical noise and power constraints, and in certain cases is computationally simpler than a traditional model. We give results to support these claims. A companion paper [14] uses the computational simplicity to explore a wide search space of algebraic factorings in a mapped network. Our own application is for continuously-sized, fullcustom designs. However, the delay model is also applicable to other methodologies, such as high-end standard...

• Type: Conference
• Year: 1995
• Where: ICCAD
• Authors: Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinatori Watanabe
• Keywords: Cell's Delay, Certain Electrical Noise, Delay Models, Hardware, ICCAD 1995