Performance Evaluation of the PowerPC 620 Microarchitecture

The PowerPC 620TM microprocessor1 is the most recent and performance leading member of the PowerPCTM family. The 64-bit PowerPC 620 microprocessor employs a two-phase branch prediction scheme, dynamic renaming for all the register files, distributed multi-entry reservation stations, true out-oforder execution by six execution units, and a completion buffer for ensuring precise exceptions. This paper presents an instruction-level performance evaluation of the 620 microarchitecture. A performance simulator is developed using the VMW (Visualization-based Microarchitecture Workbench) retargetable framework. The VMW-based simulator accurately models the microarchitecture down to the machine cycle level. Extensive trace-driven simulation is performed using the SPEC92 benchmarks. Detailed quantitative analyses of the effectiveness of all key microarchitecture features are presented.

• Type: Conference
• Year: 1995
• Where: ISCA
• Authors: Trung A. Diep, Christopher Nelson, John Paul Shen
• Keywords: Hardware, ISCA 1995, Microarchitecture, PowerPC 620 Microprocessor, Visualization-based Microarchitecture Workbench