An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays

Abstract -- Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmable gate array (FPGA) based reconfigurable coprocessor board (the Chameleon Coprocessor) being used to evaluate hardware architectures for speedup of array computation algorithms. These algorithms are developed using a Mathematics of Arrays (MOA). They provide a means to generate addresses for data transfers that require less data movement than more traditional algorithms. In this manner, the address generation algorithms are acting as an intelligent data prefetching mechanism or special purpose cache controller. Software implementations have been used to provide speedups on the order of 100% over classical methods to the solution of heat transfer equations on a uniprocessor. We extend these methods to application designs for the Chameleon Coprocessor.

• Type: Conference
• Year: 1995
• Where: ISCAS
• Authors: W. Eatherton, J. Kelly, T. Schiefelbein, H. Pottinger, L. R. Mullin, R. Ziegler
• Keywords: Chameleon Coprocessor, Field Programmable Gate Array, Hardware, ISCAS 1995, Reconfigurable Coprocessor Board