High-throughput and low-power DSP using clocked-CMOS circuitry

We argue that the clocked-CMOS (C2MOS) circuit family provides a very high throughput and low power alternative to other existing circuit techniques for the fast developing marketof portable electronics. By the virtue of self latching gates allowing very ne-grained pipelining, avoidance of precharge and short circuit power consumption, the C2MOS circuit oers very good powerdelay eciency. We support our claims through the design of an 8-bit unsigned binary multiplier with pipelining at the gate level which can produce 500 million multiplications per second consuming only 0.8 W power

• Type: Conference
• Year: 1995
• Where: ISLPED
• Authors: Manjit Borah, Robert Michael Owens, Mary Jane Irwin
• Keywords: Circuit Power Consumption, Circuit Techniques, Hardware, ISLPED 1995, Low Power Alternative