Towards a high-level power estimation capability

We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL. Such a high-level power estimation capability is required in order to provide early warning of any power problems, before the circuit-level design has been speci ed. With such early warning, the designer can explore design trade-o s at a evel of abstraction than previously possible, reducing design time and cost. Our estimator is based on the use of entropy as a measure of the average activity to be expected in the nal implementation of a circuit, given only its Boolean functional description. This technique has been implemented and tested on a variety of circuits. The empirical results to be presented are very promising and demonstrate the feasibility and utility of this approach. y This work was supported in part by Intel Corp., Santa Clara, CA. Submitted to the IEEE Transactions on CAD, 1995. 

• Type: Conference
• Year: 1995
• Where: ISLPED
• Authors: Farid N. Najm
• Keywords: Early Warning, Hardware, ISLPED 1995, Power Estimation, Power Estimation Technique