Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors

For years, the computation rate of processors has been much faster than the access rate of memory banks, and this divergence in speeds has been constantly increasing in recent years. As a result, several shared-memory multiprocessors consist of more memory banks than processors. The object of this paper is to provide a simple model (with only a few parameters) for the design and analysis of irregular parallel algorithms that will give a reasonable characterization of performance on such machines. For this purpose we extend Valiant's bulk-synchronous parallel (bsp) model with two parameters: a parameter for memory bank delay, the minimum time for servicing requests at a bank, and a parameter for memory bank expansion, the ratio of the number of banks to the number of processors. We call this model the (d x)-bsp. We show experimentally that the (d x)-bsp captures the impact of bank contention and delay on the cray C90 and J90 for irregular access patterns, without modeling machine-...

• Type: Conference
• Year: 1995
• Where: SPAA
• Authors: Guy E. Blelloch, Phillip B. Gibbons, Yossi Matias, Marco Zagha
• Keywords: D X)-bsp, Distributed And Parallel Computing, Memory Bank, Parallel Algorithms, SPAA 1995