This paper proposes a general definition of self-stabilizing wait-free shared memory objects. The definition ensures that, even in the face of processor failures, every execution after a transient memory failure is linearisable except for a bounded number of actions. Shared registers have been used extensively as communication medium in self-stabilizing protocols. We give particular attention to the self-stabilizing implementation of such registers, thus providing a large body of previous research with a more solid fundament. In particular, we prove that one cannot construct a self-stabilizing single-reader singlewriter regular bit from self-stabilizing single-reader single-writer safe bits, using only a single bit for the writer. This leads us to postulate a self-stabilizing dual-reader singlewriter safe bit as the minimal hardware needed to achieve self-stabilizing wait-free interprocess communication and synchronisation. Based on this hardware, adaptations of well known wait-free...