A Unified Approach for the Synthesis of Self-Testable Finite State Machines

-Conventionallyself-test hardware is added after synthesis is completed. For highly sequential circuits like controllersthis design method eitherleads to high hardware overheadsor compromisesfault coverage. In this paper we outlinea unified approachfor consideringself-testhardware likepattern generatorsand signatureregistersduring synthesis. Threenovel targetstructuresarepresented, and a method for designing parallel self-testable circuits is discussed in more detail.For a collectionof benchmark circuitswe show that hardware overheads for self-testable circuits can be significantlyreduced this way without sacrificingtestability.

• Type: Conference
• Year: 1991
• Where: DAC
• Authors: Bernhard Eschermann, Hans-Joachim Wunderlich
• Keywords: Computer Architecture, DAC 1991, Parallel Self-testable Circuits, Self-testable Circuits, Sequential Circuits