Layout Driven Logic Restructuring/Decomposition

As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems relegate the interconnect optimization to physical design. Physical design is, however, too far down in the design pipeline to meet the performance specifications by itself. Therefore, it is necessary for synthesis tools to share part of this optimization. In this paper, we present techniques to integrate interconnection optimization with logic restructuring and technology decomposition phases of logic synthesis. Our approach is based on a point placement of a Boolean network which is used to guide the synthesis process by providing accurate estimates on wiring area and delay. The placement solution is incrementally updated as intermediate Boolean nodes are extracted or eliminated during the decomposition or elimination procedures. Combining these techniques with layout-driven technology mapping enables us t...

• Type: Conference
• Year: 1991
• Where: ICCAD
• Authors: Massoud Pedram, Narasimha B. Bhat
• Keywords: Existing Synthesis Systems, Feature Sizes Decrease, Hardware, ICCAD 1991, Physical Design