Self-Timed Logic Using Current-Sensing Completion Detection (CSCD)

This article proposes a completion-detection method for efficiently implementing Boolean functions as self-timed logic structures. Current-Sensing Completion Detection, CSCD, allows self-timed circuits to be designed using single-rail variable encoding (one signal wire per logic variable) and implemented in about the same silicon area as an equivalent synchronous implementation. Compared to dual-rail encoding methods, CSCD can reduce the number of signal wires and transistors used by approximately 50%. CSCD implementations improved performance over equivalent dual-rail designs because of: (1) reduced parasitic capacitance, (2) removal of spacer tokens in the data stream, and (3) computation state similarity of consecutive data variables. Several CSCD configurations are described and evaluated and transistor-level implementations are provided for comparison.

• Type: Conference
• Year: 1991
• Where: ICCD
• Authors: Mark E. Dean, David L. Dill, Mark Horowitz
• Keywords: Equivalent Synchronous Implementation, Hardware, ICCD 1991, Self-timed Logic Structures, Signal Wires