Test Pattern Generation for Realistic Bridge Faults in CMOS ICs

Two approaches have been used to balance the cost of generating e ective tests for ICs and the need to increase the ICs' quality level. The rst approach favorsusing high-level fault models to reduce test generation costs at the expense of test quality, and the second approach favors the use of low-level, technology-speci c fault models to increase defect coverage but lead to unacceptably high test generation costs. In this report we (1) present the results of simulations of complete single stuck-at test sets against a low-level model of bridge defects showing that an unacceptably high percentage of such defects are not detected by the complete stuck-at test sets; (2) show how low-level bridge fault models can be incorporated into high-level test generation; and (3) describe our system for generating e ective tests for bridge faults and report on its performance. 

• Type: Conference
• Year: 1991
• Where: ITC
• Authors: F. Joel Ferguson, Tracy Larrabee
• Keywords: Fault Models, Hardware, ITC 1991, Stuck-at Test Sets, Test Generation Costs