Mitigating the Effects of RF Interference through RSSI-Based Error Recovery

On a common sensor node platform (Telos) we sample RSSI with high frequency during packet reception. We find that a packet collision (RF interference) often manifests as a measurable, temporal increase in RSSI. We investigate how the receiver can use this information to detect interference and, through temporal correlation, estimate the bit error positions in a corrupted packet. In an experimental study in two testbeds and several realistic BAN scenarios we show that a simple threshold-based algorithm often succeeds in estimating a large fraction of the bit error positions correctly. We develop an ARQ scheme that utilizes the error estimates to reduce the size of retransmitted packets. For this ARQ scheme we present an analytical model and verify it experimentally. Our results indicate that in comparison with a standard Send-and-Wait ARQ the expected number of bits per transmission can be reduced significantly (in our measurements by up to 14.7 %). Key words: Interference Mitigation; P...

• Type: Conference
• Year: 2010
• Where: EWSN
• Authors: Jan-Hinrich Hauer, Andreas Willig, Adam Wolisz
• Keywords: ARQ Scheme, Bit Error Positions, Computer Networks, EWSN 2010, Sensor Node Platform