A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation

As Field Programmable Gate Arrays (FPGAs) have reached capacities beyond millions of equivalent gates, it becomes possible to accelerate floating-point scientific computing applications. One type of calculation that is commonplace in scientific computation is the solution of systems of linear equations. A method that has proven in software to be very efficient and robust for finding such solutions is the Conjugate Gradient algorithm. In this paper we present a parallel hardware Conjugate Gradient implementation. The implementation is particularly suited for accelerating multiple small to medium sized dense systems of linear equations. Through parallelization it is possible to convert the computation time per iteration for an order n matrix from (n2 ) cycles for a software implementation to (n). I/O requirements are scalable and converge to a constant value with the increase of matrix order. Results on a VirtexII-6000 demonstrate sustained performance of 5 GFLOPS and projected results o...

• Type: Conference
• Year: 2008
• Where: ARC
• Authors: Antonio Roldao Lopes, George A. Constantinides
• Keywords: ARC 2008, Conjugate Gradient, Conjugate Gradient Implementation, Hardware, Linear Equations