Load scheduling: Reducing pressure on distributed register files for free

In this paper we describe load scheduling, a novel method that balances load among register files by residual resources. Load scheduling can reduce register pressure for clustered VLIW processors with distributed register files while not increasing VLIW scheduling length. We have implemented load scheduling in compiler for Imagine and FT64 stream processors. The result shows that the proposed technique effectively reduces the number of variables spilled to memory, and can even eliminate it. The algorithm presented in this paper is extremely efficient in embedded processor with limited register resource because it can improve registers utilization instead of increasing the requirement for the number of registers.

• Type: Conference
• Year: 2008
• Where: ASPDAC
• Authors: Mei Wen, Nan Wu, Maolin Guan, Chunyuan Zhang
• Keywords: ASPDAC 2008, Hardware, Load Scheduling, Register Files, VLIW Scheduling Length