Efficiency trends and limits from comprehensive microarchitectural adaptivity

Increasing demand for power-efficient, high-performance computing requires tuning applications and/or the underlying hardware to improve the mapping between workload heterogeneity and computational resources. To assess the potential benefits of hardware tuning, we propose a framework that leverages synergistic interactions between recent advances in (a) sampling, (b) predictive modeling, and (c) optimization heuristics. This framework enables qualitatively new capabilities in analyzing the performance and power characteristics of adaptive microarchitectures. For the first time, we are able to simultaneously consider high temporal and comprehensive spatial adaptivity. In particular, we optimize efficiency for many, short adaptive intervals and identify the best configuration of 15 parameters, which define a space of 240B points. With frequent sub-application reconfiguration and a fully reconfigurable hardware substrate, adaptive microarchitectures achieve bips3 /w efficiency gains of u...

• Type: Conference
• Year: 2008
• Where: ASPLOS
• Authors: Benjamin C. Lee, David Brooks
• Keywords: /w Efficiency Gains, Adaptive Microarchitectures, ASPLOS 2008, Programming Languages, Short Adaptive Intervals