Low power microarchitecture with instruction reuse

Power consumption has become a very important metric and challenging research topic in the design of microprocessors in the recent years. The goal of this work is to improve power efficiency of superscalar processors through instruction reuse at the execution stage. This paper proposes a new method for reusing instructions when they compose small loops: the loop's instructions are first buffered in the Reorder Buffer and reused afterwards without the need for dynamically unrolling the loop, as commonly implemented by the traditional instruction reusing techniques. The proposed method

• Type: Conference
• Year: 2008
• Where: CF
• Authors: Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras
• Keywords: Applied Computing, CF 2008, Challenging Research Topic, Instruction Reusing Techniques, Power Consumption