Low Complexity Design of High Speed Parallel Decision Feedback Equalizers

This paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. It is well known that the DFE is an efficient scheme to suppress intersymbol interference (ISI) in various communication and magnetic recording systems. However, the feedback loop within a DFE limits an upper bound of the achievable high speed in hardware implementation. A straightforward parallel implementation requires more hardware complexity. The novel proposed technique offers significant reduction of hardware complexity of 56% and 80% over the conventional parallel six-tap DFE architectures for 10 Gbps and 20 Gbps throughput, respectively.

• Type: Conference
• Year: 2006
• Where: ASAP
• Authors: Daesun Oh, Keshab K. Parhi
• Keywords: ASAP 2006, Hardware, Hardware Complexity, Parallel Six-tap Dfe, Speed Decision Feedback