Architectural support for safe software execution on embedded processors

The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and more recently, system security. Despite their limitations, the flexibility, performance, and ease of use of these languages have made them the choice of most embedded software developers. Researchers have proposed various techniques to enhance programs for memory safety; however, they are all subject to severe performance penalties, making their use impractical in most scenarios. In this paper, we present architectural enhancements to enable efficient, memory-safe execution of software on embedded processors. The key insight behind our approach is to extend embedded processors with hardware that significantly accelerates the execution of the additional computations involved in memory-safe execution. Specifically, we design custom instructions to perform various kinds of memory-safety checks and augment the inst...

• Type: Conference
• Year: 2006
• Where: CODES
• Authors: Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
• Keywords: CODES 2006, Embedded Processors, Embedded Software, Memory-safe Execution, Software Engineering