Minimizing peak current via opposite-phase clock tree

Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of the peak current caused by the clock tree. In this paper, we propose an opposite-phase scheme for peak current reduction. Our basic idea is to divide the clock buffers at each level of the clock tree into two sets: an half of clock buffers operate at the same phase of the clock source, and another half of clock buffers operate at the opposite phase of the clock source. Consequently, our approach can reduce the peak current of the clock tree nearly 50%. Experimental data consistently show that our approach works well in practice. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids – Layout, Placement and routing. General Terms Design, Reliability. Keywords Physical design, Clock network synthesis, Low power.

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
• Keywords: Clock, Clock Buffers, Clock Tree, Computer Architecture, DAC 2005